1. Field of the Invention
The present invention relates to a semiconductor device production process, and more particularly, to a production process that includes measurement of conductivity of a semiconductor device having an SOI structure.
2. Description of the Related Art
A technology referred to as SOI technology is currently used in semiconductor devices for realizing further decreases in power consumption and faster operation. When fabricating a semiconductor device using SOI technology, a semiconductor functional device is produced from a particular type of wafer, which is referred to as an SOI wafer.
An SOI wafer is a wafer having a structure in which a semiconductor layer serving as a device forming region is separated from a silicon substrate (hereinafter referred to as a support substrate) by a first insulating layer in the form of a thick silicon oxide film (hereinafter referred to as a buried oxide film). In the case of forming a semiconductor functional device on a semiconductor layer of an SOI wafer, silicon serving as a channel region and a diffusion region is completely insulated from the support substrate by the buried oxide film.
If a semiconductor functional device is formed on a semiconductor layer of an SOI wafer, the characteristics of the semiconductor functional device ends up fluctuating due to accumulation of a hot carrier in the channel region of the functional semiconductor device. The hot carrier is generated when the semiconductor functional device is turned on. In order to suppress these fluctuations, it is necessary to stabilize the operation of the semiconductor functional device by fixing the electrical potential of the channel region. A known method for fixing the electrical potential of a semiconductor functional device includes forming contact holes that penetrate the buried oxide film during the waferprocess, and embedding an electrically conductive substance in the contact holes, thereby connecting the support substrate and semiconductor functional device with the wafer surface.
In this method, since the support substrate is connected with the semiconductor functional device during the wafer process, charge generated during CVD and etching treatment or during electrostatic chuck operation ends up being input to the semiconductor functional device via the electrically conductive substance embedded in the contact holes. The charge is generated by bias of a stage applied to the support substrate during CVD and etching treatment, and bias of an electrostatic chuck applied for adsorbing the SOI wafer to the stage. Damage resulting from this input of charge that occurs during the wafer process (referred to as process-induced damage, or PID) has the risk of causing deterioration of the characteristics of the semiconductor functional device as well as the gate oxide film.
A countermeasure for this problem is known in the art. The influences of PID on semiconductor functional devices can be prevented by eliminating connection between the semiconductor functional device and support substrate during the wafer process (see Japanese Patent Application Kokai (Laid-open) No. 2006-319203 and Japanese Patent Application Kokai No. 2006-319204).
A semiconductor device disclosed in Japanese Patent Application Kokai No. 2006-319203 and Japanese Patent Application Kokai No. 2006-319204 includes an SOI wafer, an insulating layer on the SOI wafer, and an external connection pad on the insulating layer. The SOI wafer has a support substrate, buried oxide film and semiconductor layer. Substrate contacts are provided that pass through the buried oxide layer, semiconductor layer and insulating layer so as to connect the external connection pad with the support substrate. A semiconductor functional device is connected with an internal circuit pad provided on the insulating layer without being connected to the support substrate.
The use of the semiconductor device described in Japanese Patent Application Kokai No. 2006-319203 and Japanese Patent Application Kokai No. 2006-319204 makes it possible to connect the support substrate with the functional semiconductor device because a substrate connection pad on the insulating layer is connected with an internal circuit pad by wires, bonding or the like after the wafer process.
However, since the support substrate is not connected with the semiconductor functional device during the wafer process, the connection status from the external connection pad to the support substrate (to be referred to as a pin check) cannot be confirmed during probing in the wafer status. This is because measurement of conductivity between the external connection pad connected to the support substrate and internal circuit pad of the semiconductor functional device is not possible during probing in the wafer status. The pin check cannot be carried out unless the support substrate is connected to the semiconductor functional device. Work efficiency of the entire semiconductor device production process decreases since production proceeds to the next step without correcting or eliminating those devices which contain substrate contacts having defective electrical characteristics.
One approach for solving this problem includes carrying out a pin check between a prober stage and external connection pad by etching the back face of the SOI wafer and exposing the support substrate. However, since the potential for the stage potential can fluctuate depending on the status of the prober, it is difficult to accurately carry out a pin check between the stage and external connection pad.